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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
X-Ref Target - Figure 7
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 6 and Figure 7 .
FPGA O u tp u t
C REF
+
R REF V MEA S
–
d s 152_07_042109
X-Ref Target - Figure 6
V REF
Figure 7: Differential Test Setup
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
FPGA O u tp u t
R REF
V MEA S
(volt a ge level when t a king
del a y me asu rement)
C REF
(pro b e c a p a cit a nce)
Parameters V REF , R REF , C REF , and V MEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 48 .
2. Record the time to V MEAS .
d s 152_06_042109
Figure 6: Single Ended Test Setup
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V MEAS .
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 48: Output Delay Measurement Methodology
Description
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
I/O Standard
Attribute
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
HSTL_I
HSTL_II
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
LVDS_25
LVDS_25
BLVDS_25
R REF
( Ω )
1M
1M
1M
1M
50
25
50
50
25
50
50
25
50
25
100
100
100
C REF (1)
(pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V MEAS
(V)
1.25
0.9
0.75
0.75
V REF
V REF
0.9
V REF
V REF
1.1
V REF
V REF
V REF
V REF
0 (2)
0 (2)
0 (2)
V REF
(V)
0
0
0
0
0.75
0.75
1.5
0.9
0.9
1.8
0.9
0.9
1.25
1.25
1.2
1.2
0
DS152 (v3.6) March 18, 2014
Product Specification
www.xilinx.com
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